The main difference here is that the ALUs are now natively 64-bit wide. Each CU has 4x SIMD16 units and 4x Matrix Core units, with a scheduler, a 16KB 64-way L1 cache with 64B/CU/clk bandwidth, Load/Store units, and the local data share. The structure of the CUs remains largely the same as the MI100. Single MI200 Compute Unit, from the CDNA2 whitepaper Moving on, we take a look at the MI200 GCD, and the improvements it brings over the MI100. Simply put, if you can’t write code that scales well over several GPUs for some reason, it’s probably not a good fit for a supercomputing cluster. For example, Summit nodes pack six GV100 GPUs in each node, while Perlmutter‘s GPU enabled nodes have four A100 GPUs each. Multi-GPU setups are pretty common in supercomputers even if we exclude MI250X based systems. The dual die MI250X would simply be treated as two GPUs with a particularly fast link for message passing between them. HPC code is designed to scale across multiple nodes by using MPI to synchronize and pass data over high speed networks. In AMD’s favor, this disadvantage won’t be much of a factor in HPC environments. But for software that isn’t “NUMA-aware”, Intel and Biren’s GPUs can pretend to be a single GPU, allowing software to get some scaling. Just as NUMA-aware software can perform better when a multi-CPU system is set to NUMA mode (showing multiple memory pools), software aware of a multi-die GPU’s topology will be able to get the most out of the hardware. Intel’s Ponte Vecchio could so, as could Biren’s BR100. Interestingly enough, two other Hot Chips presentations showcased multi-die GPUs that could present themselves as one unified GPU. This is actually the reason AMD opted to expose the accelerators as two distinct GPUs they couldn’t match the HBM bandwidth between the two dies to be able to expose both GPUs as one, nor at least half of it to support a distributed mode configuration, so they decided to expose them as different GPUs. Second, despite being connected by 4 high-speed IF links, the chip-to-chip bandwidth is still much lower than the HBM memory bandwidth, leading to moving data between GCDs being rather painful, and significantly slower than memory accesses. This means that your algorithm needs to be multi-GPU aware in order to fully utilize the accelerator. As expected with the first gen of a new technology like this, however, it comes with multiple caveats.įirst, from a software perspective, a single accelerator is exposed as two separate GPUs. In fact, the two main MI200 accelerators (MI250, MI250X) use this approach, where each accelerator is composed of two chiplets (“GCDs” – Graphics Compute Dies) connected to each other by coherent 4x Infinity Fabric links, allowing flexibility and scalability by using multiple smaller-sized, better yielding GCDs rather than one large monolithic chip. MI250X GPU as shown in the HC34 presentation The MI200 is the second entry in the CDNA family, replacing the MI100 before it. In the GPU side, this has manifested in the divergence of gaming and compute architectures, with RDNA as the lean, latency optimized architecture tackling graphics and gaming workloads, and CDNA as the throughput optimized architecture to take on compute workloads. With the slowing down of Moore’s Law, and the ever growing processing needs of modern workloads starting to overtake the rate of generational performance increase, design houses have been forced to move to specialized, domain-specific architectures over more general one-size-fits-all approaches. Today we take a look at their latest entry into the server GPU space: the Instinct MI200 architecture. On both the server CPU and consumer sides, we have seen them break into the space with Zen and RDNA – two great designs that have both been iteratively improved on with each generation. It’s no secret that AMD has been slowly but surely executing on their plans to achieve leadership in all domains of computing.
0 Comments
Leave a Reply. |
Details
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |